Test apparatus

ABSTRACT

A test apparatus includes a test section that executes testing of each cell of the memory under test, a fail information storage section that stores fail information in a fail memory; a counting section that counts the number of defective cells in each block, a reading request receiving section that receives a request to read the fail information of each cell, a comparing section that compares the number of defective cells in a block to a predetermined reference number, a converting section that, in a case where the number of defective cells exceeds the predetermined reference value, converts a plurality of consecutive pieces of fail information in a response data string into a value indicating defectiveness, and a compressing section that compresses the response data string and returns a compressed response data string.

CROSS REFERENCE TO RELATED APPLICATION

This is a continuation application of PCT/JP2007/52851 filed on Feb. 16,2007, the contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The present invention relates to a test apparatus that tests a memory.More particularly, the present invention relates to a test apparatusthat stores information concerning defective cells acquired as a resultof a test.

2. Related Art

In manufacturing of a semiconductor device, it is essential to use adesign (DFM: Design for Manufacturing) that optimizes the efficiency ofthe manufacturing process in order to enhance yield and decrease cost.For example, when a new semiconductor device manufacturing process isimplemented, there are cases where sufficient yield cannot be achievedat a preliminary stage. In such a case, the cause of the insufficientyield is investigated and then a design of a mask pattern of an exposureapparatus is changed or an arrangement of the semiconductor device on awafer is changed. Such improvements may be required more than once,which can result in the process of investigating the cause of theproblem and solving the problem being repeated several times.

Japanese Patent Application Publication No. 1998-125092 is cited as anexample of technology that involves testing a flash memory serving asthe semiconductor device.

To increase the efficiency of the aforementioned process and beginefficient manufacturing quickly, it is desirable that the investigationof the cause of the problem be made more efficient. To facilitate theinvestigation of the cause of the problem, conventional test apparatusesfor semiconductor devices record the problem arising in thesemiconductor device for every memory cell and provide this informationto a designer. In a preliminary stage of implementing the manufacturingprocess, however, there are cases where a block in which the problemarises in only some of the cells and a block in which the problem arisesin many of the cells are mixed together in the same semiconductordevice. In the block in which the problem arises in only some of thecells, knowing the position of the cells in which the problem arises ishelpful in the investigation of the cause of the problem. On the otherhand, in the block in which the problem arises in many of the cells,knowing the position of the defective cells is not helpful ininvestigating the cause of the problem because there are cases where aphenomenon affecting the entire block is the cause of the problem.

Furthermore, because the information concerning the problem of everycell is a large amount of data, it is desirable that the information becompressed and saved. When the cells in which the problem arises arerecorded in order of the addresses, however, it is common for thecompression ratio of the data compression to decrease when the locationsat which the problem arises are many and spread out. In other words, notonly is a block with too many problems unhelpful in the investigation ofthe cause of the problem, but there is also a concern that the storagecapacity will be needlessly filled when the information concerning theproblem is stored. Therefore, recording the problem of every cell forall the blocks in a uniform manner as described above is not efficient.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein toprovide a test apparatus and a test method, which are capable ofovercoming the above drawbacks accompanying the related art. The aboveand other objects can be achieved by combinations described in theindependent claims. The dependent claims define further advantageous andexemplary combinations of the innovations herein.

According to a first aspect related to the innovations herein, oneexemplary apparatus may include a test apparatus that tests a memoryunder test. The test apparatus includes a test section that executestesting of each cell of the memory under test; a fail informationstorage section that stores in a fail memory fail informationcorresponding to each cell of the memory under test that indicatespass/fail of each cell; a counting section that counts a number ofdefective cells detected in each block for every block in the memoryunder test; a reading request receiving section that receives a requestto read the fail information of each cell included in each block; acomparing section that compares the number of defective cells in areading target block to a predetermined reference number; a convertingsection that, in a case where the number of defective cells in thereading target block exceeds the predetermined reference value, convertsinto a value indicating defectiveness a plurality of consecutive piecesof fail information in a response data string that includes the failinformation of each cell in the reading target block to be returned inresponse to the reading request; and a compressing section thatcompresses the response data string and returns the compressed responsedata string.

Furthermore, in the test apparatus, the converting section, in a casewhere the number of defective cells in the reading target block exceedsthe reference number, may output the response data string that indicatesthat all of the cells in the reading target block are defective. In thetest apparatus, the compressing section, in a case where the pluralityof consecutive pieces of fail information have the same value, mayexecute a run length compression that replaces the plurality ofconsecutive pieces of fail information with information that indicatesthe value of the fail information and a number of consecutive pieces offail information.

The test apparatus may further include a block information storagesection that stores in the block defect memory block defect informationthat indicates whether defective cells exist in the block and defectexcess information that indicates whether the number of defective cellsin the block exceeds the reference number, corresponding to each blockin the memory under test. In the test apparatus, the converting section,in a case where the defect excess information that indicates that thenumber of defective cells in the reading target block exceeds thereference number is stored in the block defect memory, may convert intoa value indicating defectiveness the plurality of consecutive pieces offail information in the response data string that includes the failinformation of each cell in the reading target block to be returned inresponse to the reading request.

The summary clause does not necessarily describe all necessary featuresof the embodiments of the present invention. The present invention mayalso be a sub-combination of the features described above. The above andother features and advantages of the present invention will become moreapparent from the following description of the embodiments taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an overall configuration of a test apparatus 10 accordingto an embodiment of the present invention.

FIG. 2 shows a specific example of an internal configuration of a memoryunder test 100 according to an embodiment of the present invention.

FIG. 3 is an example of fail information recorded in the fail memory 40of an embodiment of the present invention and shows a comparison betweena case in which the fails occur in a concentrated manner and a case inwhich the fails occur in a dispersed manner.

FIG. 4 shows a configuration having a function to store the failinformation in a defect recording module 180 according to an embodimentof the present invention.

FIG. 5 shows a configuration having a function to read the failinformation in the defect recording module 180 according to anembodiment of the present invention.

FIG. 6 is a flow chart of the process for reading the fail informationby the defect recording module 180 according to an embodiment of thepresent invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will bedescribed. The embodiments do not limit the invention according to theclaims, and all the combinations of the features described in theembodiments are not necessarily essential to means provided by aspectsof the invention.

FIG. 1 shows an overall configuration of a test apparatus 10 accordingto an embodiment of the present invention. The test apparatus 10 isprovided with a control section 110, a timing generator 120, a patterngenerator 130, a waveform shaper 140, a driver 150, a comparator 160,and a comparing section 170, each working together to operate as testsections according to the present embodiment. The test apparatus 10 isfurther provided with a defect recording module 180 that acquires a testresult and outputs the acquired test result. The timing generator 120generates a period clock that indicates one cycle of the test and a RATEsignal that indicates a start time of a test cycle by using timing datadesignated by a timing set signal (TS signal) output from the patterngenerator 130. The timing generator 120 supplies the period clock to thepattern generator 130 and supplies the RATE signal and the timing clockto the waveform shaper 140.

The pattern generator 130 generates data of a test pattern supplied tothe memory under test 100 based on the period clock and supplies thegenerated data to the waveform shaper 140. The test pattern dataincludes a test pattern made up of a signal to be supplied to the memoryunder test 100 for writing a data string onto the memory under test 100and a test pattern made up of a signal to be supplied to the memoryunder test 100 for reading the written data string from the memory undertest 100. The waveform shaper 140 writes the data string used fortesting onto a test target page of the memory under test 100. At thistime, the waveform shaper 140 shapes the data string into a waveform tobe supplied to the memory under test 100 at an appropriate timing basedon timing clock and the RATE signal.

The driver 150 supplies the test pattern data shaped by the waveformshaper 140 to the memory under test 100 as the test pattern signal. Thecomparator 160 reads the data string used for testing that is writtenonto the test target page. More specifically, the comparator 160compares an output signal output by the memory under test 100 inresponse to the test pattern to a predetermined reference voltage inorder to acquire the logic value of the output signal and sets thesequentially acquired logic values to be the data string. The comparingsection 170 compares each piece of data included in the data string readfrom the memory under test 100 in response to the test pattern to anexpected value generated in advance by the pattern generator 130. Theexpected value is the value of the data string written onto the memoryunder test 100 by the waveform shaper 140.

The defect recording module 180 receives an address from the patterngenerator 130. The defect recording module 180 also receives from thecomparing section 170 fail information, corresponding to each cell ofthe memory under test 100, that indicates pass/fail of the cell. Thedefect recording module 180 includes a fail memory 40 and stores thefail information received from the comparing section 170 in the addressin the fail memory 40 corresponding to the address received from thepattern generator 130. In other words, the pattern generator 130functions as a fail information storage section according to the presentinvention and sequentially stores fail information in the fail memory 40by sequentially supplying the addresses of the test targets to thedefect recording module 180. Furthermore, the defect recording module180 includes a block defect memory 50 that stores block defectinformation. The block defect information indicates whether a defectivecell exists in each block. The defect recording module 180 also includesa count memory 60 that stores count information. The count informationindicates the number of defective cells included in each block.

The control section 110 instructs each of the aforementioned componentsto begin the test process described above. For example, the controlsection 110 causes several test processes to be performed bysequentially instructing the timing generator 120 and, after theaforementioned processes are completed, instructs the defect recordingmodule 180 to read the test results and to output the test results to anexternal apparatus.

The test apparatus 10 according to the present embodiment outputs a testresult in which a portion is omitted that is within a range in whichanalysis of the cause of the problem occurring in the mask pattern orthe manufacturing process is not inhibited by the omission thereof. Bydoing this, the size of the data that indicates the test result isdecreased, which decreases the required capacity of a storage apparatusand the burden placed on a communication network, thereby increasing theefficiency of the analysis of the cause of the problem.

FIG. 2 shows a specific example of an internal configuration of thememory under test 100 according to an embodiment of the presentinvention. The memory under test 100 according to the present embodimentis, for example, flash memory serving as a nonvolatile memory device,and the storage region of the memory under test 100 is divided into aplurality of blocks. Each block contains, for example, a data storagecapacity of 64 KB and is formed of a plurality of pages, in this case 32pages, for example. Each block indicates a unit that can be replacedwith a backup storage region when a defect occurs. In other words, ifeach page is replaceable, each block may be configured to include onlyone page.

The memory under test 100 described as an example in the presentembodiment executes reading and writing of the data string with pageunits that have a data storage capacity of, for example, 2 KB. Morespecifically, the memory under test 100 includes, for example, aplurality of data IO terminals of 8 bits or the like, and data of oneword (e.g., 8 bits) is transmitted for every one input/output cycle viathe plurality of data IO terminals. In a single reading or writingprocess, reading or writing is executed for page units by sequentiallytransmitting each word in the page in a direction of the columns.

The storage region in the memory under test 100 includes a main area 240and an extra area 250. The main area 240 is a region that stores data210 to be stored in the memory under test 100. The extra area 250 is aregion that stores error correction code 220 for correcting a bit errorthat occurs in the data 210 and also stores control information 230 thatindicates that use of the page in which the error occurs is prohibitedor the like. When a numeric value specified as the control information230 is stored in the extra area 250, the entire block included in thecontrol information 230 is designated as being unusable and the entirepage included in the control information 230 is also designated as beingunusable. What type of setting is designated when a certain value iswritten and what settings are possible are different depending on thespecification of the memory under test 100.

FIG. 3 is an example of fail information recorded by the fail memory 40of an embodiment of the present invention and shows a comparison betweena case in which the fails occur in a concentrated manner and a case inwhich the fails occur in a dispersed manner. The horizontal axisrepresents a column direction, the vertical axis represents a pagedirection, and the diagonal lines represent the defective cells. Aplurality of consecutive address values are allocated to a plurality ofmemory cells that are consecutive in the column direction. When thedefective cells are consecutive in the column direction as shown in FIG.3( a), the addresses of the defective cells are also consecutive.Because of this, when the data is compressed by, for example, a runlength data compression or the like, the data size of the failinformation is greatly compressed because the bit data indicating amultitude of consecutive cells is compressed into a very small amount ofdata that indicates the number of consecutive cells.

On the other hand, when the defective cells are not consecutive in thecolumn direction and the quantity of defective cells is great as shownin FIG. 3( b), the addresses of the defective cells are not consecutiveand the quantity of addresses necessary to manage the defective cellsbecomes large. Because of this, it is difficult to compress the datasize of the fail information by, for example, the run length datacompression or the like because the number of consecutive cells is low.In this manner, the data size of the fail information is large when amultitude of defective cells exist in a dispersed manner, despite therebeing cases where the position of the defective cells is not important.To counter this, by using the defect recording module 180 according tothe present embodiment, the size of the overall data to be managed canbe compressed while keeping the information that is important foranalysis of the problem by compressing the fail information in adifferent format based on the content of the fail information.

FIG. 4 shows a configuration having a function to store the failinformation in the defect recording module 180 according to the presentembodiment. The defect recording module 180 includes the fail memory 40,the block defect memory 50, the count memory 60, an address selectingsection 400, an address selecting section 410, and a counting section420. The fail memory 40 stores fail information corresponding to eachmemory cell in the memory under test 100 that indicates pass/fail of thecorresponding memory cell. More specifically, the fail memory 40receives an address of a memory cell of a test target from the patterngenerator 130 and receives fail information that indicates pass/fail ofthe memory cell from the comparing section 170. The fail memory 40stores the received fail information in the address corresponding to thereceived address.

The address selecting section 400 is an example of a block informationstorage section according to the present invention. The addressselecting section 400 receives an address from the pattern generator130, generates identification information of the block associated withthe memory cell indicated by the received address by masking or the likethe lower bits, for example, of the address, and supplies the generatedidentification information to the block defect memory 50. The blockdefect memory 50 stores the fail information received from the comparingsection 170 in an address corresponding to the received identificationinformation. When the block defect memory 50 has stored fail informationindicating that a certain block is defective, the block defect memory 50continues to store the aforementioned fail information even when failinformation indicating that the aforementioned block is non-defective isreceived thereafter. By doing this, the address selecting section 400can store in the block defect memory 50 block defect informationcorresponding to each block that indicates whether defective cells existin the block.

The address selecting section 410 receives an address from the patterngenerator 130, generates identification information of the blockassociated with the memory cell indicated by the received address bymasking or the like the lower bits, for example, of the address, andsupplies the generated identification information to the count memory60. The counting section 420 incrementally increases the count valueevery time the fail information indicating that a memory cell isdefective is received from the comparing section 170. The count memory60 receives a signal that instructs storage of the count value from thepattern generator 130 every time the testing of a block is completed.The count memory 60, in response to the received signal, stores thecount value of the counting section 420 in an address corresponding tothe identification information received from the address selectingsection 410. In this way, by operating together with the addressselecting section 410 and the pattern generator 130, the countingsection 420 can count the number of defective cells detected in eachblock for every block in the memory under test 100.

FIG. 5 shows a configuration having a function to read the failinformation in the defect recording module 180 according to the presentembodiment. The defect recording module 180 further includes a readingrequest receiving section 500, a comparing section 510, a convertingsection 520, and a compressing section 530 in addition to theconfiguration shown in FIG. 4. As a first stage of a process, thereading request receiving section 500 receives from the control section110 a request to store in the block defect memory 50 the number ofdefective cells in each block. In response to the received request, thereading request receiving section 500 sequentially outputs the addressof each memory cell in each block to the address selecting section 400and the address selecting section 410. Furthermore, the reading requestreceiving section 500 outputs a reading command to the count memory 60via the address selecting section 410 in association with each addressand also outputs a writing command to the block defect memory 50 via theaddress selecting section 400 in association with each address.

Next, the address selecting section 410 generates identificationinformation of the block associated with the memory cell indicated bythe received address by masking or the like the lower bits, for example,of the address, and supplies the generated identification information tothe count memory 60. The count memory 60 outputs to the comparingsection 510 the defective cell count value stored in the addresscorresponding to the received identification information. The comparingsection 510 compares the number of defective cells in the reading targetblock to a predetermined reference number. The limit register 65 storesthe predetermined reference number. The reference number is a numberdetermined in advance by a user that indicates a number of defects thatare unacceptable from the point of view of the problem analysis. Thereference number may be changed according to the type of memory undertest 100 serving as the test target, the type of test, or the like.

Sequentially output comparison results are stored in the block defectmemory 50 as defect excess information that indicates whether the numberof defective cells in the block exceeds the reference number. Theaddress selecting section 400 generates identification information ofthe block associated with the memory cell indicated by the addressreceived by the reading request receiving section 500 by masking or thelike the lower bits, for example, of the address, and supplies thegenerated identification information to the block defect memory 50. Bydoing this, the address selecting section 400 can store the defectexcess information in an address in the block defect memory 50corresponding to the identification information.

Next, as a second stage of the process, the reading request receivingsection 500 receives from the control section 110 a request to read thefail information of each cell included in the block. In response to thereceived request, the reading request receiving section 500 sequentiallyoutputs the address of each memory cell in each block to the fail memory40 and the address selecting section 400. Furthermore, the readingrequest receiving section 500 outputs a reading command to the failmemory 40 in association with each address and outputs a reading commandto the block defect memory 50 via the address selecting section 400 inassociation with each address. It should be noted that reading of thefail memory 40 is not necessary when the number of defective cellsexceeds the reference number in all of the blocks of the memory undertest 100. In such a case, the reading request receiving section 500 neednot output the reading command to the fail memory 40.

The converting section 520 outputs to the compressing section 530 a datastring that indicates that all of the cells in a reading target blockare defective in a case where the number of defective cells in thereading target block exceeds the reference number. The convertingsection 520 is achieved by an OR gate or the like, for example. The ORgate outputs to the compressing section 530 a logical sum of the defectexcess information read from the block defect memory 50 and the failinformation read from the fail memory 40 for each block. Therefore, whendefect excess information of a certain block in which the number ofdefective cells exceeds the reference number (logic value 1) is readfrom the block defect memory 50, a signal indicating that all of thememory cells are defective is supplied to the compressing section 530,regardless of the content of the fail information supplied from the failmemory 40.

The compressing section 530 compresses the data string output in themanner described above and outputs the compressed data string to thecontrol section 110. For example, the compressing section 530 performs arun length compression on the data string and outputs the thuscompressed data string. The run length compression is a compression inwhich a plurality of consecutive pieces of fail information are replacedwith information that indicates a fail information value and a quantityof consecutive pieces of fail information when the plurality ofconsecutive pieces of fail information have the same value. Accordingly,if all of the memory cells of a certain block are defective, thecompression efficiency is extremely high, so that the size of the datastring after compression is extremely low. In this manner, the size ofthe data after compression can be caused to be extremely small bycombining the conversion process by the converting section 520 with therun length compression by the compressing section 530.

Furthermore, the process described above stores the defect excessinformation in the block defect memory 50 during the first stage andcompresses the data string based on the stored defect excess informationduring the second stage, but the two stages can be merged and performedtogether. For example, the reading request receiving section 500 maysequentially supply each address of each block along with the readingcommand to both the fail memory 40 and the count memory 60. Theconverting section 520 does not read the defect excess information fromthe block defect memory 50, but rather receives as the defect excessinformation the signals sequentially output from the comparing section510. By using such a configuration, a region for storing the defectexcess information in the block defect memory 50 becomes unnecessarybecause the defect excess information is output directly from thecomparing section 510 to the converting section 520.

FIG. 6 is a flow chart of the process for reading the fail informationby the defect recording module 180 according to an embodiment of thepresent invention. First, the timing generator 120, the patterngenerator 130, the waveform shaper 140, the driver 150, the comparator160, and the comparing section 170 operate together to perform thereading test of the memory under test 100 (S600). More specifically, atest is performed to determine whether the logic value previously storedin each memory cell of the memory under test 100 is read properly andthe result of the test is stored in the fail memory 40 as failinformation. Next, the test apparatus 10 repeats the process describedbelow for each block (S610). Hereinafter, the process target block willbe referred to as “the block.”

First, the reading request receiving section 500 causes the addressselecting section 410 to read from the count memory 60 the count valuethat indicates the number of defective cells included in the block(S620). In a case where the number of defective cells exceeds thepredetermined reference number (S630:YES), the comparing section 510stores the defect excess information indicating that the number ofdefective cells exceeds the predetermined reference number in the blockdefect memory 50 in association with the block defect information of theblock (S640). The defect excess information has a logic value of one,for example. The above process is repeated for each block (S650).

Next, the test apparatus 10 repeats the following process for each block(S 660). First, the reading request receiving section 500 causes theaddress selecting section 400 to read from the block defect memory 50the defect excess information that is stored in association with theblock defect information of the block (S670). In a case where the defectexcess information has a logic value of one, which indicates that thenumber of defective cells is greater than the reference number(S675:YES), the converting section 520 outputs a data string thatindicates that all of the cells in the block are defective (S680). Thecompressing section 530 receives the data string, compresses thereceived data string, and returns the compressed data string.

In the above description, a block is the unit that is converted to whenall of the cells are defective, but the unit may be a portion of ablock. More specifically, when the number of defective cells in a blockexceeds the reference number, the converting section 520 may convert theplurality of consecutive pieces of fail information in the response datastring to be returned to the control section 110 into a value indicatingdefectiveness in response to the reading request. In other words, theresponse data string is the fail information of each memory cell in ablock, but may also be a portion of the fail information that is theconversion target.

On the other hand, when the defect excess information has a logic valueof zero, which indicates that the number of defective cells is less thanor equal to the reference number (S675:NO), the converting section 520outputs the fail information to the compressing section 530 withoutconverting the fail information and the compressing section 530compresses the fail information and returns the compressed failinformation (S685). The test apparatus 10 repeats the above process foreach block (S690).

As made clear from the above, through the embodiments of the presentinvention, a test apparatus is realized that does not uniformly executethe same data compression for all of the blocks in the memory under test100, but rather performs data compression of all of the defective cellsfor only blocks that are not helpful in defect analysis and that are notexpected to have sufficient compression efficiency. By doing this, theanalysis of the cause of the problem can be more efficient andcomputation resources for storing or sending the information concerningthe problem can be conserved, even in a condition where the problem islikely to occur immediately after implementation of the manufacturingprocess.

While the embodiments of the present invention have been described, thetechnical scope of the invention is not limited to the above describedembodiments. It is apparent to persons skilled in the art that variousalterations and improvements can be added to the above-describedembodiments. For example, the defect excess information may be used fora repair process. Specifically, the test apparatus 10 may perform aprocess that replaces a block in which the number of defective cellsexceeds the reference number with a backup block disposed in the samememory under test 100. It is also apparent from the scope of the claimsthat the embodiments added with such alterations or improvements can beincluded in the technical scope of the invention.

1. A test apparatus that tests a memory under test, comprising: a testsection that executes testing of each cell of the memory under test; afail information storage section that stores fail informationcorresponding to each cell of the memory under test that indicatespass/fail of the cell in a fail memory; a counting section that counts anumber of defective cells detected in each block for every block in thememory under test, a block being a unit that can be replaced with abackup storage region when a defect occurs; a reading request receivingsection that receives a reading request to read the fail informationcorresponding to each cell included in a reading target block; acomparing section that compares the number of defective cells in thereading target block to a predetermined reference number and outputs acomparison result; a converting section that receives the read failinformation and the comparison result and outputs modified failinformation, of the same size as the read fail information, in which, ina case where the number of defective cells in the reading target blockexceeds the predetermined reference number, one or more pieces of failinformation indicating pass among the read fail information areconverted into fail information indicating fail; and a compressingsection that compresses the modified fail information and returns thecompressed fail information.
 2. The test apparatus according to claim 1,wherein the converting section, in a case where the number of defectivecells in the reading target block exceeds the predetermined referencenumber, outputs modified fail information that indicates that all of thecells in the reading target block are defective.
 3. The test apparatusaccording to claim 2, wherein the compressing section, in a case wherethe modified fail information includes a plurality of consecutive piecesof fail information having the same value, executes a run lengthcompression that replaces the plurality of consecutive pieces of failinformation with information that indicates the value of the pluralityof consecutive pieces of fail information and the number of consecutivepieces of fail information.
 4. The test apparatus according to claim 1,further comprising a block information storage section that stores,corresponding to each block in the memory under test, block defectinformation that indicates whether defective cells exist in a block anddefect excess information that indicates whether the number of defectivecells in the block exceeds the predetermined reference number whereinthe converting section, in a case where the defect excess informationindicates that the number of defective cells in the reading target blockexceeds the reference number, outputs modified fail information thatindicates that all of the cells in the reading target block aredefective.
 5. The test apparatus according to claim 1, wherein theconverting section, in a case where the number of defective cells in thereading target block does not exceed the predetermined reference number,outputs modified fail information that is the same as the read failinformation.